1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, the present invention relates to a memory device having a thermal conductor located between programmable volumes of the memory device.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy that is responsive to heat so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by heating the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to quickly cool to its original temperature after the heat treatment.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or “GST”) exhibits a stable and high speed transformation between amorphous and crystalline states.
FIGS. 1A and 1B illustrate an example of a memory cell 10 in a ‘set’ state and in a ‘reset’ state, respectively, and FIG. 2 is an equivalent circuit diagram of the memory cell 10 of FIGS. 1A and 1B. As shown, the memory cell 10 includes a phase-change element 11 and diode D connected in series between a bit line BL and a word line WL.
It should be noted that the structure of the phase-change element GST is presented as an example only, and that other structures may be possible. Similarly, the connections illustrated in FIGS. 1A, 1B and 2 are presented as examples only, and other configurations are possible. For example, the memory cell 10 may include the phase-change element 11 and a transistor connected in series between the bit line BL and reference potential, with the transistor gated to the word line WL.
In each of FIGS. 1A and 1B, the phase-change element 11 includes a top electrode 12 formed on a phase-change material 14 (e.g., GST). In this example, the top electrode 12 is electrically connected to a bit line BL of a PRAM memory array (not shown). A conductive bottom electrode contact (BEC) 16 is formed between the phase-change material 14 and a conductive bottom electrode 18. The diode D is electrically connected between the bottom electrode 18 and the word line WL of the PRAM cell array (not shown). Specifically, in this example, the N-junction of the diode D is connected to the word line WL and the P-junction of the diode D is connected to the bit line BL via the phase change element 11.
In FIG. 1A, the phase-change material 14 is illustrated as being in its crystalline state. As mentioned previously, this means that the memory cell 10 is in a low-resistance ‘set’ state or logic 0 state. In FIG. 1B, a portion of the phase-change material 14 is illustrated as being amorphous. Again, this means that the memory cell 10 is in a high-resistance ‘reset’ state or logic 1 state.
The set and reset states of the memory cell 10 of FIGS. 1A and 1B are establish by controlling the magnitude and duration of current flow through the BEC 16. That is, the memory cell 10 is activated (or accessed) by applying a LOW level voltage to the word line WL. When activated, the phase-change element GST is programmed according to the voltage of the bit line BL. More specifically, the bit line BL voltage is controlled to establish a programming current which causes the BEC 16 to act as a resistive heater which thermally programs the phase-change material 14 in its ‘set’ and ‘reset’ states.
FIG. 3 illustrates an example of temperature pulse characteristics of a phase-change material as the phase-change material is programmed in the ‘set’ and ‘reset’ states. In particular, reference number 1 denotes the temperature pulse of the phase-change material programmed to its ‘reset’ state, and reference number 2 denotes the temperature pulse of the phase-change material programmed to its ‘set’ state.
As shown in FIG. 3, when the phase-change material is programmed to its ‘reset’ state, the temperature of the material is increased above its melting temperature Tm (e.g., 610° C.) for a relatively short period of time, and then allowed to rapidly cool. In contrast, when the phase-change material is programmed to its ‘set’ state, the temperature of the material is increased to below its melting point Tm and above its crystallizing temperature Tc (e.g., 450° C.) for a longer period of time, and then allowed to cool more slowly. The fast and slow cooling of the ‘reset’ and ‘set’ programming operations are referred to in the art as fast “quenching” and slow “quenching”, respectively. The temperature range between the melting temperature Tm and the crystallizing temperature Tc is referred to as the “set window”.
As the integration density of the phase-change cells of PRAM devices continues to increase, thermal interference among adjacent cells has become increasingly problematic. That is, as described above in connection with FIG. 3, relatively high temperatures (˜450+° C. to 610+° C.) are needed to reliably program each cell. The resultant thermal energy of a cell being programmed can adversely influence the program state of one or more adjacent cells, thus causing inadvertent write errors in the adjacent cells. This problem is further aggravated in configurations employing so-called line type GST patterns. Here, continuous GST patterns are utilized to define the phase-change regions of multiple memory cells. Thermal interference among cells within each GST pattern represents a significant roadblock to minimizing the pitch of the phase-change cell array of the PRAM device.